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Topic starter April 1, 2022 4:07 pm
UART I2C SPI
What is UART?
- Stands for Universal Asynchronous Reception and Transmission (UART)
- A simple serial communication protocol that allows the host communicates with the auxiliary device.
- UART supports bi-directional, asynchronous and serial data transmission.
- It has two data lines, one to transmit (TX) and another to receive (RX), which are used to communicate through digital pin 0, digital pin 1.
- TX and RX are connected between two devices. (eg. USB and computer)
- UART can also handle synchronization management issues between computers and external serial devices.
How does it work?
- It can operate between devices in 3 ways:
- Simplex = data transmission in one direction
- Half-duplex = data transmission in either direction but not simultaneously
- Full-duplex = data transmission in both directions simultaneously
- Once connected, data flows from TX of the transmitting UART to RX of the receiving UART.
- As UART is an asynchronous serial transmission protocol = No clocks
- Transmitting UART converts parallel data from the master device (eg. CPU) into serial form and transmit in serial to receiving UART. It will then convert the serial data back into parallel data for the receiving device
- As UART has no clocks, UART adds start and stop bits that are being transferred to represent the start and end of a message.
- This helps the receiving UART know when to start and stop reading bits. When the receiving UART detects a start bit, it will read the bits at the defined BAUD rate.
- UART data transmission speed is referred to as BAUD Rate and is set to 115,200 by default (BAUD rate is based on symbol transmission rate, but is similar to bit rate).
- Both UARTs must operate at about the same baud rate. If the difference of BAUD rate is more than 10%, the timing of bits may be off and render the data unusable. The user must ensure UARTs are configured to transmit and receive from the same data packet.
UART Working Protocol
- A UART that is transmitting data will first receive data from a data bus that is sent by another component (eg. CPU).
- After getting the data from the data bus, it will add a start bit, a parity bit, and a stop bit to create the data packet.
- The data packet is then transmitted at the TX pin where the receiving UART will read the data packet at its RX pin. Data is sent until there is no data left in the transmitting UART.
Data Transmission and Receiving
- Once data is being transmitted by the transmit FIFO, the FIFO ‘BUSY’ flag will be asserted and active during the process.
- FIFO = First in, First out. It’s a UART buffer that that forces each byte to be passed in sequence to the receiving UART.
- The ‘BUSY’ bit will only be inactive after data is finished transmitting, the FIFO is emptied and every bit has been transmitted including the stop bit.
- When the UART receiver is idle and if the data input is low after start bit is received, the receive counter will start running and expect to receive data in the 8th cycle of BAUD16.
- If RX is still low during the 8th cycle of Baud16 while the start bit is valid, it would be processed as the wrong start bit and thus ignored.
- If the start bit is valid, data bits are sampled every 16th cycle of Baud16 based on the length of the data character. If the parity mode is enabled, the parity bit is also detected.
- If RX is high, a valid stop bit will be acknowledged. Otherwise, a framing error will occur.
- When a complete data packet is received, the data is stored in the receiving FIFO.
- The goal of interrupts is to send the content of a buffer automatically.
- User can use interrupts in the event of:
- FIFO Overflow Error
- Line-break error (RX signal remains 0 including the check and the stop bit.)
- Parity error
- Frame error (Stop bit not 1)
- Receiving timeout (receiving FIFO has data but not full and subsequent data does not transmit)
- UART module of the Stellaris family of ARM CPUs contain two 16-byte FIFOs: one for transmission and one for the reception.
- They can be configured to trigger interrupts at various depths. For example, 1/8, 1/4, 1/2, 3/4, and 7/8 depth.
- If the receiving FIFO triggers an interrupt at 1/4, a receive interrupt is triggered when the UART receives 4 data.
Working process of transmitting FIFO:
- The process is initiated as soon as data is entered. The transmission is time-consuming, thus, other data that needs to be sent can continue to enter the transmitting FIFO.
- When the transmitting FIFO is full, the user will have to wait, or you will lose your data.
- The transmitting FIFO will send the data bit by bit until the transmitting FIFO is completely empty. After transmitted data is clear, an extra slot will be added in the transmitting FIFO.
Working process of receiving FIFO:
- When the hardware receives the data, it will be stored into the receiving FIFO. The program will retrieve and erase the data automatically from the receiving FIFO, so there will be space in the receiving FIFO. If the data in the receiving FIFO is not erased and the receiving FIFO is full, the data will be lost.
- The transceiver FIFO is to solve the issue regarding the CPU being inefficient and the UART transceiver being interrupted too frequently. Using UART communication, the interrupt mode is simpler and more efficient than the polling method. With no transceiver FIFO, each data will be interrupted once and become inefficient. With a transceiver FIFO, it can generate an interrupt and constantly transmit and receive data (up to 14), which improves the transmission and reception efficiency.
- Data loss would not occur as a result of the FIFO as it has already foreseen any problems in the process of sending and receiving. As long as the UART is initialized, the interrupt routine will do everything automatically.
- UART has an internal loopback function for diagnostics or debugging where data is sent from TX will be received by the RX input.
Serial Infrared Protocol
- UART has an IrDA Serial Infrared (SIR) encoder/decoder module. The IrDA SIR module translates between an asynchronous UART data stream and a half-duplex serial SIR interface.
- It is used to provide a digital coded output and a decoded input to the UART. The UART signal pin can be connected to an infrared transceiver for the IrDA SIR physical layer connection.
Advantages of Using UART
- Simple to operate, well documented as it is a widely used method with a lot of resources online
- No clock needed
- Parity bit to allow for error checking
Disadvantages of Using UART
- Size of the data frame is limited to only 9 bits
- Cannot use multiple master systems and slaves
- Baud rates of each UART must be within 10% of each other to prevent data loss.
- Low data transmission speeds
Then there is I2C
- Stands for Inter-integrated-circuit (I2C)
- It is a serial communications protocol similarly to UART. However, it is not used for PC-device communication but instead with modules and sensors.
- It is a simple, bidirectional two-wire synchronous serial bus and requires only two wires to transmit information between devices connected to the bus.
- They are useful for projects that require many different parts (eg. sensors, pin, expansions and drivers) working together as they can connect up to 128 devices to the mainboard while maintaining a clear communication pathway!
- This is because I2C uses an address system and a shared bus = many different devices can be connected using the same wires and all data are transmitted on a single wire and have a low pin count. However, the tradeoff for this simplified wiring is that it is slower than SPI.
- Speed of I2C is also dependent by data speed, wire quality and external noise
- The I2C protocol is also used as a two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
How does it work?
- It has 2 Lines which are SCL (serial clock line) and SDA (serial data line acceptance port)
- CL is the clock line for synchronizing transmission. SDA is the data line through which bits of data are sent or received.
- The master device initiates the bus transfer of data and generates a clock to open the transferred device and any addressed device is considered a slave device.
- The relationship between master and slave devices, transmitting and receiving on the bus is not constant. It depends on the direction of data transfer at the time.
- If the master wants to send data to the slave, the master must first address the slave before sending any data.
- The master will then terminate the data transfer. If the master wants to receive data from the slave, the master must again address the slave first.
- The host then receives the data sent by the slave and finally, the receiver terminates the receiving process. The host is also responsible for generating the timing clock and terminating the data transfer.
- It is also necessary to connect the power supply through a pull-up resistor. When the bus is idle, both lines operate on a high power level.
- The capacitance in the line will affect the bus transmission speed. As the current power on the bus is small, when the capacitance is too large, it may cause transmission errors. Thus, its load capacity must be 400pF, so the allowable length of the bus and the number of connected devices can be estimated.
I2C Working Protocol
Data Transmission Method
- The master sends the transmitting signal to every connected slave by switching the SDA line from a high voltage level to a low voltage level and SCL line from high to low after switching the SDA line.
- The master sends each slave the 7 or 10-bit address of the slave and a read/write bit to the slave it wants to communicate with.
- The slave will then compare the address with its own. If the address matches, the slave returns an ACK bit which switches the SDA line low for one bit. If the address does not match its address, the slave leaves the SDA line high
- The master will then send or receive the data frame. After each data frame has been transferred, the receiving device returns another ACK bit to the sender to acknowledge successful transmission.
- To stop the data transmission, the master sends a stop signal to the slave by switching SCL high before switching SDA high
- All masters generate their own clocks on the SCL line to transmit messages on the I2C bus.
- Data is only valid during the high period of the clock.
- Clock synchronization is performed by connecting the I2C interface to the SCL line where the switch goes from high to low. Once the device’s clock goes low, it keeps the SCL line in this state until it reaches the high level of the clock.
- If another clock is still in a low period, the low-to-high switch does not change the state of the SCL line. The SCL line is always held low by the device with the longest low period. At this time, the device with a short and low period will enter a high and waiting state.
- When all relevant devices have completed their low period, the clock line goes high.
- After that, there is no difference in the state of the device clock and the SCL line, and all devices begin to count their high period. The device that first completes the high period will pull the SCL line low again.
- The low period of the synchronous SCL clock is determined by the device with the longest low clock period, while the high period is determined by the device with the shortest high clock period.
- Fast mode devices can receive and transmit at 400kbit/s. They have to be able to synchronize with a 400kbit/s transmission and extend the low period of the SCL signal to slow down the transmission.
- Fast mode devices are backwards compatible and can communicate with standard mode devices from 0 to 100 kbit/s I2C bus systems. However, as standard mode devices are not upward compatible, they cannot operate in a fast I2C bus system. The fast mode I2C bus specification has the following characteristics compared to the standard mode:
- The maximum bit rate is increased to 400 kbit/s;
- Adjusted the timing of the serial data (SDA) and serial clock (SCL) signals.
- Has the function of suppressing glitch and the SDA and SCL inputs have Schmitt triggers.
- The output buffer has a slope control function for the falling edges of the SDA and SCL signals
- Once the power supply of the fast mode device is turned off, the I/O pins of SDA and SCL must be left idle and cannot block the bus.
- The external pull-up device connected to the bus must be tuned to accommodate the shortest maximum allowable rise time of the fast mode I2C bus. For buses with a maximum load of 200pF, the pull-up device of each bus can be a resistor. For a bus with a load between 200pF and 400pF, the pull-up device can be a current source (maximum 3mA) or a switched resistor circuit.
- Hs mode devices can transmit information at bit rates up to 3.4 Mbit/s and remain fully backwards compatible with fast mode or standard mode (F/S mode) devices that can communicate bi-directionally in a speed mixed bus system.
- The Hs mode transmission has the same serial bus principle and data format as the F/S mode system except for arbitration and clock synchronization which is not performed.
- The I2C bus specification in high-speed mode is as follows:
- In high speed (Hs) mode, the master device has an open-drain output buffer for the high-speed (SDAH) signal and an open-drain pull-down and current source pull-up circuit at the high-speed serial clock (SCLH) output. This shortens the rise time of the SCLH signal and at any time, only one host current source is active;
- In the Hs mode of a multi-master system, arbitration and clock synchronization are not performed in order to speed up the bit processing capability. The arbitration process normally ends after the host code is transmitted in the F/S mode.
- The Hs mode master device generates a high and low serial clock signal with a ratio of 1:2 which removes the timing requirements for setup and hold time.
- The Hs mode device can have a built-in bridge. During Hs mode transmission, the SDAH and SCLH lines of the Hs mode device are separated from the SDA and SCL lines which reduces the capacitive loading of the SDAH and SCLH lines and make rise and fall faster.
- The difference between Hs mode slave devices and F/S slave devices is the speed at which they operate.
- The Hs mode device can suppress glitches, and the SDAH and SCLH outputs also have a Schmitt trigger;
- The output buffer of the Hs mode device has a slope control function for the falling edges of the SDAH and SCLH signals.
Advantages of using I2C
- Has a low pin/signal count even with numerous devices on the bus
- Flexible, as it supports multi-master and multi slave communication.
- Simple as it only uses 2 bidirectional wires to establish communication among multiple devices.
- Adaptable as it can adapt to the needs of various slave devices.
- Support multiple masters.
Disadvantages of using I2C
- Slower speed as it requires pull-up resistors rather than push-pull resistors used by SPI. It also has an open-drain design = limited speed.
- Requires more space as the resistors consume valuable PCB real estate.
- May become complex as the number of devices increases.
What is SPI?
- Stands for Serial Peripheral Interface (SPI)
- It is similar to I2C and it is a different form of serial-communications protocol specially designed for microcontrollers to connect.
- Operates at full-duplex where data can be sent and received simultaneously.
- Operate at faster data transmission rates = 8Mbits or more
- It is typically faster than I2C due to the simple protocol. Even if data/clock lines are shared between devices, each device will require a unique address wire.
- Used in places where speed is important. (eg. SD cards, display modules or when info updates and changes quickly like thermometers)
How does it work?
- Communicate with 2 ways:
- Selecting each device with a Chip Select line. A separate Chip Select line is required for each device. This is the most common way RPi’s currently use SPI.
- Daisy chaining where each device is connected to the other through its data out to the data in line of the next.
- There is no limit to the number of SPI device that can be connected. However, there are practical limits due to the number of hardware select lines available on the main device with the chip select method or the complexity of passing data through devices in the daisy-chaining method.
- In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex communication, which is simple and efficient.
SPI Working Protocol
- The SPI communicates via 4 ports which are:
- MOSI – Master Data Output, Slave Data Input
- MISO – master data input, slave data output
- SCLK – clock signal, generated by the master device, up to fPCLK/2, slave mode frequency up to fCPU/2
- NSS – Slave enabled signal, controlled by the master device, some ICs will be labelled as CS (Chip select)
- In a multi-slave system, each slave requires a separate enable signal, which is slightly more complicated on hardware than the I2C system.
- The SPI interface is actually two simple shift registers in the internal hardware. The transmitted data is 8 bits. It is transmitted bit by bit under the slave enable signal and shift pulse generated by the master device. The high bit is in the front and the low bit is in the back.
- The SPI interface is synchronous serial data transmission between the CPU and the peripheral low-speed device. Under the shift pulse of the master device, the data is transmitted bit by bit. The high bit is in the front and the low bit is in the back. It is full-duplex communication, and the data transmission speed is overall faster than the I2C bus and can reach speeds of a few Mbps.
Advantages of using SPI
- The protocol is simple as there is no complicated slave addressing system like I2C.
- It is the fastest protocol compared to UART and I2C.
- No start and stop bits unlike UART which means data can be transmitted continuously without interruption
- Separate MISO and MOSI lines which means data can be transmitted and received at the same time
Disadvantages of using SPI
- More Pin ports are occupied, the practical limit to a number of devices.
- There is no flow control specified, and no acknowledgement mechanism confirms whether data is received unlike I2C
- Uses four lines – MOSI, MISO, NCLK, NSS
- No form of error check unlike in UART (using parity bit)
- Only 1 master
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